(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of preventing poly-2 residue that typically remains in place under a layer of poly-1 oxide in applications where two layers of poly are used to form a gate electrode, such as in Charge Coupled Device (CCD) applications.
(2) Description of the Prior Art
In the manufacturing of semiconductor devices a number of different but interacting disciplines are used that collectively create high performance semiconductor devices. The majority of these semiconductor devices have as function the processing of digital information, which is characterized by zero and one conditions, typically created by on-off conditions of switching transistors. In addition, hybrid functions can be provided that address not only the processing of digital signals but also address the processing of analog signals, either as a function that is provided by one analog semiconductor device or in collaboration with digital devices. Device performance improvements have been sought and established by continuously decreasing device dimensions, concurrently increasing device packaging density. This poses problems for a number of the typical analog components such as capacitors and inductors that have physical dimensions that do not lend themselves to ready integration into a highly miniaturized, sub-micron device environment.
The mixing of functions and processing capabilities results in a mixing of components that coexist within one semiconductor device. It is therefore not uncommon to see resistors and capacitors that form part of a semiconductor device, which does not negate that the vast majority of device components is made up of transistors, gate electrodes and a variety of switching components that address logic processing functions. Capacitors can for instance form a basic component of analog circuits that are used for analog applications such as switched capacitor filters. Capacitors are also widely applied in digital applications such as the storage node for Dynamic Random Access Memory (DRAM) circuits. This ability of capacitors to function in either the digital or the analog mode is referred to as the mixed mode application of the capacitor.
The DRAM technology is widely used for data storage where one transistor and one capacitor form one DRAM cell. For the capacitor a stacked capacitor is frequently used, since this structure has good data storage performance characteristics combined with low surface space requirements. To fabricate a DRAM device, a modified CMOS process is typically used. One other application in which the CMOS structure has been successfully applied is in the creation of image sensors. An image sensor is, in its broadest terms, used to convert an optical image that is focused on the sensor into electrical signals. The image sensor typically includes an array of light detecting elements, where each element produces a signal corresponding to the intensity of light impinging on that element when an image is focused on the array. These signals may then be used, for example, to display a corresponding image on a monitor or may otherwise be used to provide information about the optical image.
One frequently used type of image sensor is a charge-coupled device (CCD). Integrated circuit chips containing CCD image sensors have a relatively low yield and are expensive due to the specialized processing involved. CCD devices also consume a relatively large amount of power.
A much less expensive type of image sensor can be formed as an integrated circuit by using a CMOS process. In such a CMOS type image sensor, a photodiode or phototransistor (or any other suitable device) is used as the light-detecting element, where the conductivity of the element corresponds to the intensity of light impinging on the element. The variable signal thus generated by the light detecting element is an analog signal with a magnitude that is approximately proportional (within a certain range) to the amount of light that impinges on the element.
Light-detecting elements are typically formed in a two-dimensional core array, which is addressable by row and column. Once a row of elements has been addressed, the analog signals from each of the light detecting elements in the row are coupled to the respective columns in the array. An analog-to-digital converter may then be used to convert the analog signals of the columns to digital signals so as to provide only digital signals at the output of the image sensor chip.
What is needed is an inexpensive, but highly efficient, image sensor, which produces reliable images. Implied in this is that leakage current in the spacer regions, that is the source/drain regions of the CMOS gate electrode of the image sensor, is reduced to a minimum. Potential plasma damage that can be caused during the spacer etching must therefore be kept at a minimum.
Conventional semiconductor CCD image sensors often employ a double polysilicon gate structure that forms a gate electrode array structure. Such a structure has a first polysilicon gate electrode that is separated from a second polysilicon gate electrode by a thin insulation layer of silicon dioxide. The first poly electrode is slightly overlapped by the second poly electrode. The systematic variations of potential that are applied to these electrodes, which are referred to as clocking, permits the device to function. In the case of a frame transfer CCD image sensor, light passes through the poly electrodes and creates electronic hole pairs in the underlying silicon. By clocking electrodes, the accumulated electrons are moved under adjacent electrodes. Light must pass through the polysilicon electrodes in order to accumulate charge. However, polysilicon is not entirely transparent, which results in a reduction of sensitivity and a spectral response of the image sensor.
FIGS. 1a through 1e show a Prior Art gate electrode with the etching of the spacer, as follows:
FIG. 1a shows the polysilicon (poly-1) gate electrode 10 that has been created over the top surface of a layer 14 of ONO. FIG. 1a shows the initial processing steps to create a gate electrode, as follows:
ONO layer 14 deposition PA1 poly-1 layer 10 deposition, and PA1 patterning and etching of layer 10 of poly-1 applying a dry etch thereby forming the initial stage of the gate electrode PA1 1) FIG. 1b, a wet thermal oxidation of the surface of the created layer 10 of poly-1 thereby creating a poly oxidation layer 12; layer 12 of oxidized poly-1 serves as a layer of Inter Poly Oxide (IPO) that separates two layers of poly, that is layer 10 of poly-1 and there thereover deposited PA1 2) FIG. 1c, layer 16 of poly-2, and PA1 3) FIG. 1d, the application of a poly-2 (layer 16, FIG. 1c) dry etch thereby creating the spacers 17 for the gate electrode 10. PA1 20 is the surface of a silicon substrate over which a gate electrode is to be formed PA1 22 is a field isolation region that defines that active region in the surface of the silicon substrate 20 PA1 24 is a deposited and patterned layer of poly-1 that forms the body of the gate electrode PA1 26 is the layer of IPO that has been formed using a wet thermal oxidation process PA1 28 is the layer of inter poly oxide (IPO) that has been formed over the surface of the layer 24 of poly-1; and PA1 30 is the poly-2 residue that remains in place under the poly-1 layer 24 after dry etching of the layer 28 of poly-2, this dry etch is performed to create the gate electrode including the gate spacers on the sidewalls of the layer 24 of poly-1.
FIG. 1b through 1d show the results of performing:
Although typically the layer 16 (FIG. 1c) of poly-2 can be etched by applying a wet etch, there are semiconductor manufacturing facilities where the process of wet etch of polysilicon is no longer available in advanced Integrated Circuit facilities and where therefore a dry etch must be performed for the layer 16 of poly-2. This latter etch of the layer 16 of poly-2 creates, as already stated, the spacers for the poly-1 gate electrode 10, whereby deposits 18 of poly-2, FIG. 1d, remain in place raising the potential of causing electrical shorts between adjacent poly-2 gates 15, FIG. 1e. The process of the invention therefore provides a method whereby the layer of poly-2 can be etched applying a dry etch where this application of the dry etch does however not result in poly-2 residue remaining in place adjacent to the gate spacers and therefore prevents the poly-2 of gate 15 from connecting (shorting) with adjacent poly-2 gates through the path of the poly-2 residue 18.
The problems that have been experienced following the processing sequence that is shown in FIGS. 1a through id has been highlighted in FIG. 1d, where poly-2 residue 18 remains in place. This process does apply the method of dry etch for the etch of the layer 16 of poly-2. It is desired to continue to be able to use the dry etch for the spacer formation, however it is not acceptable that this dry etch results in poly-2 residue remaining in place adjacent to the spacer of the gate electrode. The poly-2 residue 18 reduces the isolation of the gate electrodes that is typically provided by the gate spacers on the sidewalls of the gate electrode 10. This reduction in isolation has resulted in shorts between the adjacent gate electrodes 15, FIG. 1e. The process of the invention provides a method whereby residue 18 is, among other advantages, eliminated.
FIG. 1e further shows a top view of the regions where the residual poly-2 forms whereby regions 11 and 13 indicate the regions of opposite adjacency to the gate electrodes 15 where the problem of residual poly-2 is most typically observed. The cross sections that have been shown in FIGS. 1a through 1d are cross sections that have been taken along the line A-A' of FIG. 1e.
FIG. 2 further shows the poly-2 that remains in place under the poly-1, the regions that have been highlighted in FIG. 2 are as follows:
U.S. Pat. No. 6,015,730 (Wang et al.) shows a SAC process.
U.S. Pat. No. 5,998,249 (Liaw et al.) shows a dram SAC process and spacers.
U.S. Pat. No. 5,114,872 (Roselle et al.) teaches a contact process with SiN spacers.
U.S. Pat. No. 5,366,913 (Nakao) shows an oxide sidewall process.
U.S. Pat. No. 5,516,716 (Hawkins et al.) discloses a Charge Coupled Device (CCD) process.